The present invention relates to a defect analyzer and a defect analyzing method.
In the manufacturing process of a semiconductor device, a number of elements having patterns formed in multiple layers are fabricated on a semiconductor wafer. The completed elements undergo tests on electrical characteristics and defective items are removed from an assembling process. In the manufacturing process of a semiconductor device, yields are quite important and test results on the electrical characteristics are fed back to the manufacturing process and are used for the management of each process.
However, the manufacturing process of a semiconductor device is made up of a number of steps and it takes quite a long time from the start of manufacturing to tests on electrical characteristics. Thus even when defects are found in the manufacturing process through the tests on electrical characteristics, a number of wafers are being processed at that time, so that the tests results cannot be sufficiently used for improving yields.
Thus defect tests for testing formed patterns in the steps of a process (for example, for each layer) and detecting defects (including a foreign matter and a faulty pattern) have been conducted. The defect tests in the multiple steps of the overall process make it possible to quickly detect the occurrence of a defect, so that test results can be immediately reflected in process management.
The defect tests are conducted by emitting test light to a wafer, condensing reflected light through a lens, forming an image with an image sensor, and comparing the image with a reference image. The intensity of reflection of test light varies among patterns on the wafer. When the tests are conducted at the same light level while the intensity of received light has a constant threshold value for identifying defects, a region where a defect is likely to be detected (high sensitivity region) and a region where a defect is unlikely to be detected (low sensitivity region) appear. Thus for example, in memory products including a small number of cells with simple shapes, the defect tests are conducted while different sensitivities are manually set for cell portions and surrounding circuit portions through visual observations of wafers.
However, in the case of logic products having random patterns, a number of high sensitivity regions and low sensitivity regions are scattered and thus sensitivity setting has been quite difficult. For this reason, in logic products, wafers are entirely tested at the same sensitivity and defect data outputted as test results varies in information quality (accuracy) among regions.
When data with information quality varying among test regions is simultaneously handled as it is, the accuracy of the subsequent defect analysis including the prediction of yields may decrease.
Defects are broadly divided into random defects caused by dust generated from manufacturing equipment and systematic defects caused by a mismatch in a manufacturing process and a pattern design. These defects are desirably handled in a classified manner because of completely different occurrence mechanisms and solutions.
As a technique for classifying these defects, a method is known in which the clustering degree of a defect detected in a defect test is determined using a distance from an adjacent defect and a random component and a clustering component are separated from each other.
In this conventional technique, however, when defects are caused by multiple factors on a wafer and when systematic defects (defects which look like a random distribution and are caused by a process margin) not having regionality are present, the defects cannot be classified with high accuracy, thereby reducing the accuracy of defect analysis.